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| TP112 100Base-TX/FX Converter Feature n n n n n General Description The TP112 is a single chip media converter for 100Base-TX to 100Base-FX. The TP112 support one 100Base-TX port over CAT5 twisted pair cable and one ECL interface to connect with fiber module to apply in 100Base-TX/FX converter application. On the 100Base-TX side, The TP112 is directly connected to external transformers The chip performs data recovery, clock recovery, adaptive equalization, auto negotiation, and baseline wander correction function. The TP112 is compliant with the IEEE 802.3u standard. 100Base-TX IEEE 802.3u compatible Full and Half duplex with Auto-negotiation Fully integrated adaptive equalizers 125MHz clock generator and clock recovery Include transmit waveform shaping to reduce EMI and filter Include baseline wander correction Support one TX interface and one Fiber module interface(ECL interface). Support transmit, receive/link, full duplex LED Single 5 Voltage supply operation 128-pin PQFP n n n n n Typical Application n 100Base-TX to 100Base-FX Converter FX Fiber Module TP112 TX 1 TP112-DS-P02 Jan 5, 2000 TP112 PIN Assignments AGND TXOM AGND AGND AGND AGND AGND AGND AGND AGND AVCC AVCC AVCC AVCC AVCC AVCC AGND AVCC NC NC NC 128 127 126 125 124 123 121 120 119 118 NC 117 116 115 114 113 112 111 110 109 108 107 106 105 104 122 103 AVCC TXOP RXIM RXIP FXRDP FXRDM FXSD AVCC AVCC NC FXTDM FXTDP AGND BGRES BGGND AVCC DVCC DGND FORCEON DVCC DVCC HALFONLY TMODE NC NC NC DVCC NC DVCC DVCC FXTLED* FXLRLED* DGND TXER1 TXD31 TXD21 TXD11 TXD01 TXCLK1 MDC MDIO NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 AGND AGND NC NC AVCC AVCC NC NC NC AGND DVCC OSCI/X1 X2 DGNC DVCC DGND DVCC DGND NC DVCC NC NC RESET* TXLED* LRLED* DVCC RXD00 RXD10 RXD20 RXD30 RXCLK0 DGND RXER0 FDXLED* NC NC NC RXDV0 TP112 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 TXEN1 DVCC TXEN0 RXER1 TXER0 NC NC DVCC RXD31 RXD21 RXD11 RXD01 TXCLK0 TXD20 TXD30 DGND DGND NC RXCLK1 RXDV1 TXD00 TXD10 DVCC DVCC 2 TP112-DS-P02 Jan 5, 2000 DGND NC TP112 PIN Description TYPE I O I/O O DESCRIPTION Used as Input pin Used as Output pin Used as Input and Output pin Used as Output with Open Drain LABEL RXIP,RXIM TXOP,TXOM FXRDP,FXRDM TYPE I O I DESCRIPTION Receiver Pair Differential data from external transformers RD pair. Transmit Pair Differential data to external transformers TD pair. Fiber Receiver Data Pair Used to receiver the data from the fiber transceiver module, need external pull high resistor and pull low resistor, depend on impedance match of the fiber transceiver module. Fiber Transmit Data Pair It used as output the data into the fiber transceiver module, need external pull high resistor and pull low resistor, depend on impedance match of the fiber transceiver module. Fiber Signal Detect Used as an input pin from the Fiber transceiver module to indicate a valid signal quality had been detect. Transmit Error Active high. When an error happened in the transmit data stream. Transmit Enable Active high. Indicate 4B data valid on TXD[3:0] Transmit Clock Output is 25MHz continuous clock. Transmit Data Input 4B transmit data. Receive Data valid Active high. Indicates that a received frame is in progress, and data on RXD pin is valid Receive Error It Indicate that there's an error during a receive frame when high Receive Clock 25MHz output. The clock is recovered from the incoming data on the cable inputs Receive Data Output 4B data output and synchronously to RXCLK. PIN NO. Media Connections 104,105 111,110 1,2 8,7 FXTDP,FXTDM O 3 MII Interface 59 30 52 39 53 35 58,57,56,55 31,32,33,34 65 45 70 46 72 47 73,74,75,76 48,49,50,51 FXSD I TXER0 TXER1 TXEN0 TXEN1 TXCLK0 TXCLK1 TXD[3:0]0 TXD[3:0]1 RXDV0 RXDV1 RXER0 RXER1 RXCLK0 RXCLK1 RXD[3:0]0 RXD[3:0]1 I I I/O I O3s O O O 3 TP112-DS-P02 Jan 5, 2000 TP112 PIN Description (continued) PIN NO. Modes 36 37 19 LABEL MDC MDIO TMODE TYPE I I/O I DESCRIPTION Management Data Clock MII management data clock input, maximum clock rate is 2.5MHz Management Data I/O MII management data input/output Test Mode Active high. Set TP112 into test mode, and low for normal operation. There's an internal pull low resistor so default is normal operation Half Duplex Mode Only 1: half duplex 0: full duplex Force Mode Enable 1: force mode enable 0: auto negotiation mode enable Full Duplex LED Before link OK, this pin is tri-stated. After link OK this pin indicate current duplex operation for TP112. High for half duplex and low for full duplex Link/Receive LED Active low. Indicates the link status of the port, driven low when link to the port is good. Output for 20mS clock while the TP112 is receiving data from external media Transmit LED Active low. Indicates that data is being transmitting Reset Active low. Reset TP112, remain low at least 1us. Oscillator input or crystal input (25MHz50ppm). Crystal output. Leave it unconnected (i.e., as a NC pin) when oscillator is used. Band Gap Resistor A 6.2KOhm 1% resistor that supply 200uA reference current for receive Band Gap Resistor Ground Band gap resistor ground reference input 18 15 LEDs 69 HALFONLY FORCEON I/IPL I/IPL FDXLED* O 78 28 79 27 Reset & Clock 80 91 90 Current Reference 10 11 LRLED* FXLRLED* TXLED* FXTLED* RESET* OSCI/X1 X2 BGRES BGGND O O I I O I I 4 TP112-DS-P02 Jan 5, 2000 TP112 PIN Description (continued) PIN NO. Power & Ground 4,5,12,97,98, 103,108,112, 114,117,116 121,126 9,93,101,102, 106,107,109, 113,115,120, 122,123,127, 128 13,16,17,23, 25,26,41,43, 61,62,77,83, 86,88,92, 14,29, 42,54,63,71, 85,87,89 6,20,21,22,24, 38,40,44,60,64, 66,67,68,81,82, 84,94,95,96, 99,100,118,119, 124,125 LABEL AVCC TYPE I Analog VCC +5V Analog Ground 0V DESCRIPTION AGND I DVCC I Digital VCC +5V Digital Ground 0V No Connection DGND NC I 5 TP112-DS-P02 Jan 5, 2000 TP112 Absolute Maximum Rating Supply Voltage ....................... VCC -0.25 to VDD +0.25V Storage Temperature ....................................-65 to 150C Ambient Operating Temperature (Ta).................0 to 70C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation under these conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect product reliability. Electrical n Operating Conditions Parameter Sym. AVCC DVCC ICC Min. 4.75 4.75 Typ. 5 5 TBD Max. 5.25 5.25 Unit V V W Conditions VCC=5.0V Supply Voltage Power Consumption n Input Clock Parameter Sym. Min. -50 Typ. 25 Max. +50 Unit MHz PPM Conditions Frequency Frequency Tolerance n I/O Electrical Characteristics I I O O Sym. VIL VIH VOL VOH Min. 2.0 0.4 2.4 Typ. Max. 0.8 Unit V V V V Conditions Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High voltage n IOH=4mA, VCC=5.0V IOL=4mA, VCC=5.0V TX Transceiver Electrical Characteristics Parameter Sym. VP TRF TRFS VO Min. Typ. Transmitter 0.95 1.0 98 100 3 4 Max. 1.05 102 5 0.5 0.5 5 Unit V % ns ns ns % Conditions Peak Differential Output Voltage Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot 6 TP112-DS-P02 Jan 5, 2000 TP112 Order Information Part No. TP112 PIN 128 PIN PQFP Notice - 7 TP112-DS-P02 Jan 5, 2000 TP112 Package Detail QFP 128L Outline Dimensions Unit: Inches/mm HD D 128 103 1 102 38 39 64 65 e b GAGE PLANE A2 c HE E L1 y L Symbol A1 A2 b c HD D HE E e L L1 y Dimensions In Inches Min. 0.010 0.107 0.007 0.004 0.669 0.547 0.906 0.783 0.025 0 Nom. 0.014 0.112 0.009 0.006 0.677 0.551 0.913 0.787 0.020 0.035 0.063 Max. 0.018 0.117 0.011 0.008 0.685 0.555 0.921 0.791 0.041 0.004 12 D A1 Dimensions In mm Min. 0.25 2.73 0.17 0.09 17.00 13.90 23.00 19.90 0.65 0 Nom. 0.35 2.85 0.22 0.15 17.20 14.00 23.20 20.00 0.50 0.88 1.60 Max. 0.45 2.97 0.27 0.20 17.40 14.10 23.40 20.10 1.03 0.10 12 Note: 1. Dimension D & E do not include mold protrusion. 2. Dimension B does not include dambar protrusion. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 8 TP112-DS-P02 Jan 5, 2000 |
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